About Me

Hi there! My name is Yiqiu (Susan) Sun. I'm a final-year Computer Science PhD student at University of Illinois Urbana-Champaign, expecting to graduate in May 2027. I am fortunate to be advised by Prof. Saugata Ghose. My dissertation tackles the memory wall by making in-memory computing hardware, which performs computation directly inside memory arrays, more programmable, efficient and accurate.

Throughout my PhD, I have found my passion for the following topics:
Memory Systems Performance Engineering Distributed Algorithms (workload balancing) Parallel Programming Models (and languages) Data Formats (precision and arithmetic)

Previously, I received B.S.E. in Computer Engineering from University of Michigan, where I worked with Prof. John P. Hayes and Prof. Trevor Mudge. I also received B.E. in Electrical and Computer Engineering from Shanghai Jiao Tong University (UM-SJTU Joint Institute).

I am on the industry job market for roles starting in summer 2027. Feel free to reach out!

Office: Room 224, CSL Building, 1308 W Main Street MC 228, Urbana, IL, 61801
Email: yiqiu3@illinois.edu

Work Experience

Standard Kernel Co., Member of Technical Staff, Palo Alto, CA (May 2026 - Jul 2026)
Multi-GPU LLM inference profiling (vLLM, SGLang) · FP4/FP8 CUTLASS MoE GEMM and all-reduce optimization · In-context kernel timing and critical-path tooling
Performance Engineering Distributed Algorithms Data Formats

NVIDIA, GPU Architecture PhD Intern, Santa Clara, CA (May 2025 - Aug 2025)
Interconnect scalability · Traffic profiling and visualization · Cross-team hardware-software co-design
Performance Engineering

Samsung Semiconductor, Storage Systems Research Intern, San Jose, CA (May 2023 - Aug 2023)
CXL-SSD caching · Embedding-table lookup latency for recommender systems · Patent
Memory Systems Performance Engineering

Selected Publications

“The Memory Processing Unit: A Generalized Interface for End-to-End In-Memory Execution,” 2026 IEEE International Symposium on High-Performance Computer Architecture (HPCA),
M. S. Q. Truong, Y. Sun, D. Xiong, A. Shah, A. Glass, A. Farrell, J. A. Bain, L. R. Carley and S. Ghose
[link]
Memory Systems Parallel Programming

“MapReduce Framework for Processing-Using-Memory,” 2024 ACM Student Research Competition at the International Conference on Parallel Architectures and Compilation Techniques (PACT), Poster
Y. Sun
Parallel Programming Memory Systems

“Tutorial on Simulation for Processing-Using-Memory Systems,” 2024 International Symposium on Computer Architecture (ISCA), Tutorial
ARCANA Research Group, Sandia National Laboratories
[link]
Memory Systems

“Benefits of Stochastic Computing in Hearing Aid Filterbank Design,” 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS)
T. J. Baker, Y. Sun and J. P. Hayes
[link]
Data Formats

Research Projects

Dissertation Work

Organization of in-memory computing hardware

The in-memory computing architecture my dissertation is based on.

MaRIMBA: A Parallel Programming Model for In-Memory Computing

Design a MapReduce-style programming model and runtime that automates work partitioning, data placement, and communication scheduling across DRAM, ReRAM, and wafer-scale SRAM in-memory computing hardware.

Parallel Programming Distributed Algorithms Memory Systems

BONGO: Replication-Aware Matrix Multiplication

Model and partition matrix multiplication on in-memory computing hardware by trading operand replication against limited memory capacity and communication cost.

Distributed Algorithms Performance Engineering Memory Systems

FLUTE: Flexible-Precision Arithmetic (in progress)

Co-design flexible-precision floating-point arithmetic with numerical algorithms such as Strassen to explore precision, performance, and accuracy trade-offs.

Data Formats Memory Systems

Other Works

Support End-to-End Execution for Processing-Using-Memory

Co-develop the memory processing unit (MPU), a common interface that lets software run end to end on different in-memory computing designs.

Memory Systems Parallel Programming

Analyzing the Impact of Processing-in-Memory Devices on Scene Reconstruction in Robotics

Evaluate two different depth fusion algorithms executing on a conventional CPU + memory system and a Hybrid Memory Cube with standard CPU cores.

Memory Systems Performance Engineering

Scheduling Algorithms and Optimizations for Lowering Python Package APIs to AI Engine Array

Schedule high-level NumPy logic onto AI engines, establish specialized performance modeling for AI engines and design a more exhaustive FFT design space than polyhedral model.
Picture credit to Xilinx.

Parallel Programming Performance Engineering

Misc

1. During my spare time, I love playing chess, running, and climbing!
2. My favourite color is green.